I am a postdoctoral researcher at EPCC, the UK national supercomputing centre, and the University of Edinburgh, specialising in hardware-efficient AI, performance portability, and energy efficiency on novel accelerator architectures.

My research focuses on deploying and optimising ML systems across a diverse range of accelerators, including AMD/Nvidia GPUs, Cerebras Wafer Scale Engine, AMD Xilinx AI Engines, and Tenstorrent devices, with applications in fintech and the legal domain.

Prior to this, my PhD in High-Performance Computing focused on accelerating quantitative finance workloads on Field-Programmable Gate Arrays (FPGAs). This involved recasting Von Neumann-based CPU algorithms into dataflow-style designs suited to FPGA execution, and implementing these in C/C++ via High-Level Synthesis (HLS) across recent Intel and AMD Xilinx platforms, benchmarking results against x86 and GPU baselines.

In mid-2021, I started collaborating with STAC Research, the industry-standard financial benchmarking organisation, to explore the acceleration of their benchmark suite on reconfigurable architectures. I am interested in heterogeneous computing, novel architectures, and all things HPC.

Before my PhD, I worked as a Systems Architect in the financial services sector and studied at Mannheim University in Germany. I have a background in economics and finance, and I graduated with a master’s in High-Performance Computing from EPCC in 2019 with a project on scaling GPU inference for a segmentation task in weather forecasting.

You can find my publications on Google Scholar. If you would like to reach out to me, please send an email or contact me on Linkedin.